DESY, with its 2700 employees at its two locations in Hamburg and Zeuthen, is one of the world’s leading research centres. Its research focuses on decoding the structure and function of matter, from the smallest particles of the universe to the building blocks of life. In this way, DESY contributes to solving the major questions and urgent challenges facing science, society and industry. With its ultramodern research infrastructure, its interdisciplinary research platforms and its international networks, DESY offers a highly attractive working environment in the fields of science, technology and administration as well as for the education of highly qualified young scientists.
The Photon-Science Detector Group designs and builds innovative and state-of-the-art area detectors for the photon sources in Hamburg and world-wide. The group works in close collaboration with world leading research groups in photon-science, as well as with other detector groups world-wide. We are currently developing a new generation readout system for our PERCIVAL soft X-ray imager. For this we are looking for an experienced FPGA design engineer.
About the role:
- Develop Firmware on Xilinx Ultrascale+ FPGAs for data handling of fast imagers (serialisation, processing and packaging)
- Testing of Firmware performance using existing lmager and data backend
- Documentation of firmware
Good reasons to join:
Look forward to a unique working environment on our international research campus. We attach particular importance to appreciative cooperation and the well-being of our DESY employees. You will benefit from our family-friendly and collegial atmosphere, our established health management and occupational pension provision. As a public employer, we offer you a secure workplace and facilitate your individual career with our comprehensive training and development opportunities. Remuneration according to the collective labour agreement (TV-AVH).
To be successful in this role:
- Master`s or Engineer`s degree in electronic engineering, or computer science or equivalent qualification
- Experience in VHDL and System Verilog and Xilinx Vivado design flow
- Experience with Xilinx 7 series and Ultrascale/Ustrascale+ FPGA families
- Good knowledge of Scripting languages Python, TCL and programing in C/C++
- Knowledge of English and excellent team player
For further information please contact Prof. Dr. Heinz Graafsma, +49 40 8998 1678 (firstname.lastname@example.org).
We look forward to receiving your application via our application portal:
DESY promotes the professional development of women and therefore strongly encourages women to apply for the position to be filled. In addition, severely handicapped persons with equal aptitude are given preferential consideration. The advertised positions are basically suitable for part-time employment.
You can find further information here:
Deutsches Elektronen-Synchrotron DESY
Phone: +49 40 8998-3392
Deadline for applications: 30.04.2021
To apply for this job please visit v22.desy.de.