Multilayer stack opens door to low-power electronics

Researchers found that a stack of ultrathin materials, characterized in part at the Advanced Light Source (ALS), exhibits a phenomenon called negative capacitance, which reduces the voltage required for transistor operation.

The material is fully compatible with today’s silicon-based technology and is capable of reducing power consumption without sacrificing transistor size or performance.

High efficiency, low disruption

Microelectronics is expected to account for about 5% of total electricity production by 2030 thanks to ever-increasing demands for information processing. Maintaining progress will require a fundamental shift toward more efficient devices, with an emphasis on materials compatible with state-of-the-art silicon technology.

The phenomenon of negative capacitance represents one possible solution, promising to significantly reduce power consumption in electronic devices while fitting seamlessly into current semiconductor protocols. In this work, researchers took a key step toward integrating negative capacitance into advanced transistors, with support from various government and industrial groups including Samsung, Intel, SK hynix, Applied Materials, and DARPA.

Inside the gate

A transistor is essentially an on-off switch for the flow of current through a semiconductor, activated by a small voltage from a “gate” electrode. A thin insulating layer (the gate oxide) separates the semiconductor from the gate. Increasing the gate oxide’s ability to store charge (i.e., its capacitance) lowers the transistor’s operating voltage and thus reduces overall power consumption.

In advanced silicon transistors, the gate oxide is a combination of silicon oxide (SiO2) and hafnium oxide (HfO2). In this work, researchers replaced the HfO2 with a multilayered stack that displays negative capacitance—a counterintuitive effect in which decreasing the gate voltage increases the stored charge on the gate oxide, thus maintaining performance at reduced power.

Read more on the Berkeley Laboratory website

Image: Artistic rendering of a multilayered structure that exhibits negative capacitance, integrated onto a silicon chip. Incorporating this material into advanced silicon transistors could make devices more energy efficient.

Credit: Ella Maru Studio/UC Berkeley