Redox-based memristive devices are one of the most attractive emerging memory technologies.
…in terms of scaling, power consumption and speed. In these devices, external electrical stimuli cause changes of the resistance of an oxide layer sandwiched between two metal electrodes. In the simplest application, the device can be set into a low resistance state (LRS) and reset into a high resistance state (HRS), which may encode a logical one and zero, respectively. The major obstacle delaying large-scale application, however, is the large cycle-to-cycle (C2C) and device-to-device (D2D) variability of both LRS and HRS resistance values. These variabilities describe the stochastic nature of the switching process within one cell, resulting in different resistances obtained for each switching cycle and different resistances obtained for different cells on the same chip.
Image:(a) Schematic of the device geometry. A SrTiO3 layer (blue) is sandwiched between a Nb:SrTiO3 bottom electrode (dark grey) and graphene top electrode (grey honeycomb lattice). The graphene electrode is contacted through a metal lead, which is electrically separated from the continuous bottom electrode, allowing for biasing inside PEEM instruments. (b) Quasistatic I-V curve of a representative graphene/SrTiO3/Nb:SrTiO3 device. The bottom electrode serves as virtual ground, while the bias is applied to the graphene top electrode. (c) PEEM image of a graphene/Al2O3/SrTiO3 device in the LRS at an electron energy E – EF of 3.4 eV. Scale bar, 5 µm. (d) PEEM image of the same device after Reset. (e) and (f) PEEM images after one additional Set and Reset operation, respectively. Insets: magnified photoemission threshold map of the area around the conductive filament. The maps were obtained by fitting the threshold spectrum for each pixel.